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| SSM9926TGO N-CHANNEL ENHANCEMENT MODE 8 POWER MOSFET A PRODUCT SUMMARY Low on-resistance Capable of 2.5V gate drive Surface mount package G1 S1 t D1 D2 G2 S2 DESCRIPTION The Advanced Power MOSFETs from Silicon Standard Corp. provide the designer with the best combination of fast switching, ruggedized device design, ultra low on-resistance and cost-effectiveness. BVDSS RDS(ON) ID 8 G2 20V 32m 4.7A Pb-free; RoHS-compliant S2 D2 S2 G1 TSSOP-8 S1 D1 S1 ABSOLUTE MAXIMUM RATINGS Symbol VDS VGS ID@TA=25 ID@TA=70 IDM PD@TA=25 TSTG TJ Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Continuous Drain Current Pulsed Drain Current 1 3 3 Rating 20 12 4.7 3.8 20 1 0.008 -55 to 150 -55 to 150 Units V V A A A W W/ Total Power Dissipation Linear Derating Factor Storage Temperature Range Operating Junction Temperature Range THERMAL DATA T Symbol Rthj-a Parameter Thermal Resistance Junction-ambient 3 Value Max. 125 Unit /W 03/11/2007 Rev.1.00 D www.SiliconStandard.com 1 SSM9926TGO A ELECTRICAL CHARACTERISTICS Symbol BVDSS BVDSS/Tj RDS(ON) Parameter Drain-Source Breakdown Voltage @Tj=25 C(unless otherwise specified) o Test Conditions VGS=0V, ID=250uA Min. 20 0.5 - Typ. 0.03 12 9 2 4 8 10 16 7 550 120 94 1.2 Max. Units 32 45 1.2 1 25 100 15 880 1.9 V V/ m m V S uA uA nA nC nC nC ns ns ns ns pF pF pF Breakdown Voltage Temperature Coefficient Reference to 25, ID=1mA Static Drain-Source On-Resistance 2 VGS=4.5V, ID=4A VGS=2.5V, ID=2A VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Rg Gate Threshold Voltage Forward Transconductance Drain-Source Leakage Current (Tj=25oC) Drain-Source Leakage Current (Tj=70oC) VDS=VGS, ID=250uA VDS=5V, ID=6A VDS=20V, VGS=0V VDS=16V ,VGS=0V VGS=12V ID=6A VDS=16V VGS=4.5V VDS=10V ID=1A RG=3.3,VGS=5V RD=10 VGS=0V VDS=20V f=1.0MHz f=1.0MHz Gate-Source Leakage Total Gate Charge 2 Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate Resistance 2 SOURCE-DRAIN DIODE Symbol VSD trr Qrr Parameter Forward On Voltage 2 2 Test Conditions IS=1.7A, VGS=0V IS=6A, VGS=0V, dI/dt=100A/s Min. - Typ. 15 8 Max. Units 1.2 V ns nC Reverse Recovery Time Reverse Recovery Charge Notes: 1.Pulse width limited by Max. junction temperature. 2.Pulse width <300us , duty cycle <2%. 2 3.Surface mounted on 1 in copper pad of FR4 board ; 208/W when mounted on Min. copper pad. 03/11/2007 Rev.1.00 www.SiliconStandard.com 2 SSM9926TGO 30 30 TA=25 C 25 o 5.0V 4.5V 3.5V 2.5V ID , Drain Current (A) T A =150 C 25 o 5.0V 4.5V 3.5V ID , Drain Current (A) 20 20 15 15 2.5V 10 10 5 5 V G =1.5V 0 0 1 2 3 0 V G =1.5V 0 1 2 3 V DS , Drain-to-Source Voltage (V) V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 50 1.6 ID=2A T A =25 o C 40 1.4 ID=4A V G =4.5V Normalized R DS(ON) 0 2 4 6 8 10 RDS(ON) (m ) 1.2 1.0 30 0.8 20 0.6 -50 0 50 100 150 V GS , Gate-to-Source Voltage (V) T j , Junction Temperature ( C) o Fig 3. On-Resistance v.s. Gate Voltage Fig 4. Normalized On-Resistance v.s. Junction Temperature 1.6 6 4 Normalized VGS(th) (V) 1.2 1.2 IS(A) T j =150 o C 2 T j =25 o C 0.8 0 0 0.2 0.4 0.6 0.8 1 0.4 -50 0 50 100 150 V SD , Source-to-Drain Voltage (V) T j , Junction Temperature ( C) o Fig 5. Forward Characteristic of Reverse Diode 03/11/2007 Rev.1.00 Fig 6. Gate Threshold Voltage v.s. Junction Temperature 3 www.SiliconStandard.com A 15 1000 SSM9926TGO f=1.0MHz I D =6A VGS , Gate to Source Voltage (V) 12 C iss C (pF) 9 V DS =10V V DS =12V V DS =16V 100 C oss C rss 6 3 0 0 5 10 15 20 10 1 5 9 13 17 21 25 29 Q G , Total Gate Charge (nC) V DS , Drain-to-Source Voltage (V) Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics Normalized Thermal Response (Rthja) 100 1 Duty factor=0.5 0.2 10 100us 1ms ID (A) 1 0.1 0.1 0.05 10ms 100ms 0.02 0.01 PDM 0.01 Single Pulse t T Duty factor = t/T Peak Tj = PDM x Rthja + Ta Rthja=208oC/W 0.1 T A =25 C Single Pulse o 1s DC 0.01 0.1 1 10 100 0.001 0.0001 0.001 0.01 0.1 1 10 100 1000 V DS , Drain-to-Source Voltage (V) t , Pulse Width (s) Fig 9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance VDS 90% VG QG 4.5V QGS QGD 10% VGS td(on) tr td(off) tf Charge Q Fig 11. Switching Time Waveform 03/11/2007 Rev.1.00 Fig 12. Gate Charge Waveform 4 www.SiliconStandard.com SSM9926TGO Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, expressed or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 03/11/2007 Rev.1.00 www.SiliconStandard.com 5 |
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